How to Reduce the Decoupling Induction in PCB’s
Decoupling is often a poorly understood term that creates problems in designing an efficient printed circuit board (PCB). Decoupling capacitors are used to ‘decouple’ or separate one part of the circuit from another. You can imagine it as a forced separation between fighting, noisy couples.
The main role of the decoupling capacitor is to reduce the high-frequency noise generated by power supply signals. The capacitor takes tiny voltage ripples out of the voltage supply that prevents damage to the delicate ICs.
One issue with the decoupling capacitor is inductance. In this article, you will learn what exactly is decoupling inductance and how to resolve this issue.
About Decoupling Inductance
Inductance is a main problem that must be overcome for efficient performance of decoupling capacitors. This is important to ensure that the capacitors perform efficiently at higher frequencies of up to hundreds of megahertz.
The decoupling capacitor inductance can be reduced by careful placement of the vias and plane layers. Let’s take a look at how one can minimize the inductance through these two techniques.
1. Reduce Decoupling Induction by Proper Placement of Vias
Proper distance between the two vias is a critical factor that can help improve decoupling performance. There are various ways in which the vias can be placed for optimum performance. In the figure below, you can see three alternate placements of the vias labelled as good, better, and the best.
The good placement simply uses shorter traces for connection with the capacitor. The inductance reduction performance can be improved further by placing the vias side by side. However, the best performance is achieved if you place the vias sideways on the top and bottom as shown in the figure.
2. Reduce Decoupling Induction by Proper Placement of Decoupling Caps
Another method that can be used to reduce the decoupling inductance is through optimizing the placement of the decoupling caps. Here are some tips that can help in reducing the decoupling inductance in PCBs.
- The decoupling caps should be placed on top of one another
- Maximum number of high-speed ICs should be placed on one side — either the top or the bottom
- Ground and power planes should be placed on adjacent layers and close to the top layer. This is important otherwise it will result in a significant loss of distributed capacitance.
You should note is that that this technique is only applicable for a PCB with more than four layers. With a PCB with four or less layers, the decoupling caps will always remain close to one and far from another due to which you can’t optimize the digital design of the circuit.
In conclusion, the inductive portion of a PCB is limited by the inductance from the IC pads to the planes. Proper placement of the vias and decoupling caps is important to reduce this inductance. Minimizing the loop area formed by the vias and the planes will improve the performance of the decoupling capacitor throughout the PCB.